1. Field of the Invention
The present invention relates to a power semiconductor device manufactured using at least two types of unleaded solders, and also relates to a method of manufacturing such a semiconductor device.
2. Background Art
Power semiconductor devices are made up, e.g., of a power semiconductor element, such as an IGBT or a high voltage diode, packaged in a resin case. An exemplary power semiconductor device will be described with reference to FIG. 17. FIG. 17 omits the resin case of the power semiconductor device to illustrate the way in which the power semiconductor element is soldered. As shown in FIG. 17, circuit patterns 202 and 204 are formed on the top surface of a ceramic substrate 200. A power semiconductor element 214 is bonded to the circuit pattern 202 by a first step solder 210. The first step solder 210 has a composition of 95 wt % Sn-5 wt % Sb, where wt % is the abbreviation for weight percent. Further, an electrode terminal 220 is bonded to the circuit pattern 204 by a second step solder 218. The second step solder 218 has a composition of 96.5 wt % Sn-3 wt % Ag-0.5 wt % Cu.
On the other hand, a bottom surface pattern 206 is formed on the bottom surface of the ceramic substrate 200. A heat sink 216 is bonded to the bottom surface pattern 206 by a first step solder 212. The heat sink 216 is covered with electrolytic Ni plating. It should be noted that all of the circuit patterns 202 and 204 and the bottom surface pattern 206 are Cu patterns covered with electroless Ni—P plating (hereinafter referred to simply as “Ni—P plating”). The ceramic substrate 200, the circuit patterns 202 and 204, and the bottom surface pattern 206 are sometimes referred to collectively as the “insulating substrate 208.”
Two steps of reflow soldering are required to complete the manufacture of power semiconductor devices having such a configuration. Specifically, the first step solders 210 and 212 are melted in the first reflow soldering step, so that the power semiconductor element 214 and the heat sink 216 are bonded to the circuit patterns 202 and the bottom surface pattern 206, respectively. The second step solder 218, on the other hand, is melted in the second reflow soldering step, so that an electrode terminal 220 inserted into the resin case is bonded to the circuit pattern 204.
It should be noted that the temperature in the second reflow soldering step must be such that the first step solders 210 and 212 do not remelt. The reason is that if the first step solders 210 and 212 remelt in the second reflow soldering step, defects may result such as tilting and displacement of the power semiconductor element 214 and the insulating substrate 208 and run-out of solder. That is, the solidus temperature of the first step solders 210 and 212 must be sufficiently higher than the liquidus temperature of the second step solder 218. The solidus temperature is the temperature at which melted solder completely solidifies on gradual cooling. The liquidus temperature, on the other hand, is the temperature at which solidified solder completely melts on gradual heating. In the above example, the first step solders 210 and 212 have a solidus temperature of 240° C., and the second step solder 218 has a liquidus temperature of 220° C. Therefore, remelting of the first step solders 210 and 212 can be avoided in the second reflow soldering step. (See, for example, Japanese Patent Laid-Open No. 09-181125, No. 10-286689, No. 10-193171, No. 2001-144111, No. 2001-244622, and No. 2009-60101.)
When the first step solders 210 and 212 are made of binary Sn—Sb solder alloy, as in the above example, Ni is likely to diffuse from the Ni—P plating of the circuit pattern 202 and the bottom surface pattern 206 into these solders in the reflow soldering steps. If this Ni diffusion into the first step solders 210 and 212 progresses, then Cu adjacent the Ni—P plating moves into voids left by the diffused Ni. As a result, small gaps called “Kirkendall voids” are formed at the interface between Cu and the Ni—P plating. It has been found that this may lead to peeling of the Ni—P plating due to heat cycles, resulting in degradation of the heat dissipation characteristics of the semiconductor element.
Further, the diffusion of Ni from the Ni—P plating into the solders results in an increase in the P concentration of the Ni—P plating (becoming relatively rich in P). This has resulted in degradation of the bonding reliability of the Ni—P plating.
An example of the diffusion of Ni into solder will be described with reference to FIG. 18. FIG. 18 is a diagram showing profile or contour lines extracted from a cross-sectional SEM image of the area surrounding the interface between the bottom surface Cu pattern and the Ni—P plating thereon, wherein this SEM image was taken after the power semiconductor device was maintained at 175° C. for 200 hours in a high temperature storage evaluation test. FIG. 18 shows that Ni has diffused from the Ni—P plating into the solder resulting in the formation of a gap or void at the interface between the bottom surface Cu pattern and the Ni—P plating due to delamination of the Ni—P plating. Further, the remaining thickness of the Ni—P plating was 0.6 μm, although the original thickness of the Ni—P plating immediately after its formation was 4 μm. Furthermore, the entire portion of the remaining 0.6-μm thick Ni—P plating was richer in P than it was before it was subjected to this high temperature storage evaluation test. Although the diffusion of Ni into solder has been described in connection with the Ni—P plating of the pattern on the bottom surface of the insulating substrate, it is to be understood that the same problem also occurs with the Ni—P plating of the patterns on the top surface of the insulating substrate.
It will be noted that the thinner the Ni—P plating, the greater the decrease in its bonding reliability due to the problem of Ni diffusion described above. In order to avoid an excessive decrease in the bonding reliability of the Ni—P plating, the Ni—P plating may be formed to a thickness of approximately 5 μm, although its typical thickness is approximately 2 μm. However, an increase in the thickness of the Ni—P plating may result in a reduction in the productivity of the plating process performed by the manufacturer of the insulating substrate, as well as an increase in the cost of the insulating substrate. Further, it has been found that increasing the thickness of the Ni—P plating alone may not be sufficient to achieve a high level of reliability. That is, the above reliability problem is not fundamentally solved by increasing the thickness of the Ni—P plating.